arm: socfpga: cache: Enable D-Cache

The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.

Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>

diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index 41498421c1fbbef1ba566ca4145183dc61e8a7f8..6b982778be0780146a5cebc6f5137a4579d2dc65 100644 (file)
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -35,6 +35,7 @@ int board_early_init_f(void)
 int board_init(void)
 {
        icache_enable();
+       dcache_enable();
 
        /* Address of boot parameters for ATAG (if ATAG is used) */
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 76979b10b868e8be90b98cb8bbbc0ed3ec62bf9f..de60bb2f069f36d03673c373ab8597a73bd5d268 100644 (file)
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -18,7 +18,6 @@
 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
 
 #define CONFIG_ARMV7
-#define CONFIG_SYS_DCACHE_OFF
 #undef CONFIG_USE_IRQ
 
 #define CONFIG_MISC_INIT_R
@@ -26,6 +25,7 @@
 #define CONFIG_SOCFPGA
 #define CONFIG_CLOCKS
 
+#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
 #define CONFIG_SYS_CACHELINE_SIZE      32
 
 /* base address for .text section */